Research
My research focuses on Digital VLSI design, Computer architecture, and EDA physical synthesis. Currently my research group designs processors and data-parallel accelerators using both RTL and high-level synthesis design flows.
Data parallel accelerators for Machine Learning
- Systolic architectures with reduced latency for integer and reduced-precision floating point arithmetic
- Selective data encoding for low power data streaming in systolic architectures
- Optimized buffering for spatial variants of CNN accelerators
- Systolic Three Matrix Multiplier for Graph Convolutional Networks
DRiM: DUTH RISC-V Microprocessors
Computer Arithmetic
Network on Chip
- NoCpad: SystemC HLS infrastucture for building scalable industry-grade cache-coherent NoCs
- Efficient in-network multicasting
- Low cost clock domain crossing
EDA physical synthesis
- Machine learning based physical synthesis flow tuning
- OCV-aware clock tree optimization
Awards and Honors
- Best Student Paper Award for my PhD students Christodoulos Peltekis and Kosmas Alexandridis at IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) 2024 for the paper "Reusing Softmax Hardware Unit for GELU Computation in Transformers"
- Best Student Paper Award for my PhD student D. Mangiras - Electronics, Circuits and Systems Track of Modern Circuits and Systems Technologies (MOCAST) conference for the paper "Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment", July 2021.
- Best Paper Award - T track in Design Automation and Test in Europe conferene for the paper "Error-Shielded Register Renaming Subsystem for a Dynamically Scheduled Out-of-Order Core” March 2019. photo
- EDAA Outstanding Dissertation Award 2018 to my PhD student Anastasios Psarras in "Topic 2 – New directions in system-on-chip platforms co-design, novel emerging architectures and system-level management" for his PhD thesis "High-performance Networks-on-Chip". photoA photoB
- Second position to the timing optimization constest organized by the TAU workshop - ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2019. photo
- Hipeac technology transfer award "Network-on-Chip for Think Silicon’s ultra-low-power GPU", 2015.
- Best Paper Award - D track in Design Automation and Test in Europe conferene for the paper "PhaseNoC: TDM Scheduling at the Virtual-Channel Level for Efficient Network Traffic Isolation", March 2015. photoA photoB
Publications
Journal Papers
K. Alexandridis, G. Dimitrakopoulos, "Online Alignment and Addition in Multi-Term Floating-Point Adders" in IEEE Transactions on VLSI Systems, accepted Oct. 2024. paper
D. Filippas, C. Peltekis, V. Titopoulos, I. Kansizoglou, G. Sirakoulis, A. Gasteratos, G. Dimitrakopoulos, "A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators", in IEEE Access, 2024. paper
C. Peltekis, V. Titopoulos, C. Nicopoulos, G. Dimitrakopoulos, "DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity" in IEEE Computer Architecture Letters, 2024. paper
A. Stefanidis, I. Zoumpoulidou, D. Filippas, G. Dimitrakopoulos, G. Ch. Sirakoulis, "Synthesis of Approximate Parallel Prefix Adders" , in IEEE Transactions on VLSI Systems, vol. 31, no. 11, pp. 1686-1699, Nov. 2023, paper
C. Peltekis, D. Filippas, G. Dimitrakopoulos, C. Nicopoulos, "Exploiting Data Encoding and Reordering for Low-Power Streaming in Systolic Arrays" in Microprocessors and Microsystems, Elsevier, Oct. 2023. paper
K. Rallis, I.-A. Fyrigos, P. Dimitrakis, G. Dimitrakopoulos, I. Karafyllidis, A. Rubio, G. Ch. Sirakoulis, "A Reprogrammable Graphene Nanoribbon-based Logic Gate" in IEEE Transactions on Nanotechnology, vol.22, pp. 684-695, Oct. 2023. paper
D. Mangiras, D. Chinnery, G. Dimitrakopoulos, "Task-based Parallel Programming for Gate Sizing" in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 4, pp. 1309-1322, April 2023. paper
D. Filippas, C. Nicopoulos, and G. Dimitrakopoulos, "Streaming Dilated Convolution Engine", in IEEE Transactions on VLSI Systems, vol. 31, no. 3, pp. 401-405, March 2023. paper
D. Filippas, C. Nicopoulos, and G. Dimitrakopoulos, "Templatized Fused Vector Floating-Point Dot Product for High-Level Synthesis", in Journal of Low Power Electronics and Applications, 12(4), 2022. paper
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D. Filippas, N. Margomenos, N. Mitianoudis, C. Nicopoulos, and G. Dimitrakopoulos, "Low-Cost On-Line Convolution Checksum Checker" , in IEEE Transactions on VLSI Systems, vol. 30, no. 2, Feb. 2022. paper
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D. Mangiras, G. Dimitrakopoulos, "Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment" , Technologies, 2021, 9(4):92. paper
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G. Dimitrakopoulos, K. Papachatzopoulos, and V. Paliouras, "Sum Propagate Adders", in IEEE Transactions on Emerging Topics in Computing (Special Section on Emerging and Impacting Trends on Computer Arithmetic), vol. 9, no. 3, pp. 1479-1488, July-Sept. 2021 paper
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A. Stefanidis, D. Mangiras, C. Nicopoulos, D. Chinnery, G. Dimitrakopoulos "Autonomous Application of Netlist Transformations inside Lagrangian Relaxation-based Optimization" , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 8, pp. 1672-1686, Aug. 2021. paper
D. Konstantinou, C. Nicopoulos, J. Lee, and G. Dimitrakopoulos, "Multicast-enabled Network-on-Chip Routers leveraging Partitioned Allocation and Switching” , in Integration: the VLSI journal, Elsevier, vol. 77, pp. 104-112, 2021. paper
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D. Mangiras, A. Stefanidis, I. Seitanidis, C. Nicopoulos, G. Dimitrakopoulos "Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering" , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 10 , Oct. 2020, pp. 2835 - 2848. paper
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D. Konstantinou, A. Psarras, C. Nicopoulos, G. Dimitrakopoulos "The Mesochronous Dual-Clock FIFO Buffer" , in IEEE Transactions on VLSI Systems, vol. 28, no. 1, pp. 302-306, Jan. 2020 paper
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I. Seitanidis, G. Dimitrakopoulos, P. Mattheakis, L. Masse-Navette, D. Chinnery, "Timing-Driven and Placement-Aware Multi-Bit Register Composition" , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 8., pp. 1501-1514, Aug., 2019. paper
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I. Seitanidis, C. Nicopoulos, G. Dimitrakopoulos, "Automatic Generation of Peak-Power Traffic for Networks-on-Chip" , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no.1, pp. 96-108, Jan., 2019. paper
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K. Patsidis, D. Konstantinou, C. Nicopoulos, G. Dimitrakopoulos, "A Low-Cost Synthesizable RISC-V Dual-Issue Processor Core Leveraging the Compressed Instruction Set Extension" , in Microprocessors and Microsystems, Elsevier, Sept. 2018. paper
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A. Psarras, S. Moisidis, C. Nicopoulos, G. Dimitrakopoulos, "Networks-on-Chip with Double-Data-Rate Links" , in IEEE Transactions on Circuits and Systems I, vol. 64, no. 12, pp. 3103-3114, Dec. 2017. paper
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A. Psarras, M. Paschou, C. Nicopoulos, G. Dimitrakopoulos, "A Dual-Clock Multiple-Queue Shared Buffer", in IEEE Transactions on Computers, vol. 66, no. 10, pp. 1809 - 1815, Oct. 2017. paper
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E. Karampasis, N. Papanikolaou, D. Voglitsis, M. Loupis, A. Psarras, A. Boubaris, D. Baros, G. Dimitrakopoulos, "Active Thermoelectric Cooling Solutions for Airspace Applications: the THERMICOOL Project", in IEEE Access, 2017. paper
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A. Psarras, I. Seitanidis, C. Nicopoulos, G. Dimitrakopoulos "ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing", in IEEE Transactions on Computers, vol. 65, no. 10, pp. 3136-3147, Oct. 2016. paper
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K. Chrysanthou, P. Englezakis, A. Prodromou, A. Panteli, C. Nicopoulos ,Y. Sazeides, G. Dimitrakopoulos, "An On-Line and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures" , in ACM Transactions on Architecture and Code optimisation (TACO), Vol. 13, No. 2, June 2016. paper
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A. Psarras, J. Lee, I. Seitanidis, C. Nicopoulos, G. Dimitrakopoulos "PhaseNoC: Versatile Network Traffic Isolation through TDM-Scheduled Virtual Channels", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.35, no.5, pp.844-857, May 2016. paper
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I. Seitanidis, A. Psarras, K. Chrysanthou, C. Nicopoulos, G. Dimitrakopoulos "ElastiStore: Flexible Elastic Buffering for Virtual-Channel-based Networks-on-Chip", in IEEE Transactions on VLSI Systems, vol.23, no.12, pp.3015-3028, Dec. 2015. paper
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D. Bertozzi, G. Dimitrakopoulos, J. Flich, S. Sonntag, "The fast evolving landscape of on-chip communication", in Design Automation of Embedded Systems, Springer, vol. 19, no. 1-2, March 2015, pp. 59-76. paper
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G. Dimitrakopoulos, E. Kalligeros, K. Galanopoulos “Merged Switch Allocation and Traversal in Network-On-Chip Switches”, in IEEE Transactions on Computers, Oct. 2013, pp. 2001-2012. paper
D. S. Gracia, G. Dimitrakopoulos, T. Monreal Arnal, M. G.H. Katevenis, and V. Vinals Yufera “LP-NUCA: Networks-in-Cache for high-performance low-power embedded processors”, in IEEE Transactions on VLSI Systems. vol.20, no.8, pp. 1510-1523, Aug. 2012. paper
H. T. Vergos, G. Dimitrakopoulos “On modulo 2n+1 adder design”, in IEEE Transactions on Computers, vol.61, no.2, pp. 173-186, Feb. 2012. paper
N. Chrysos, G. Dimitrakopoulos “Practical High-Throughput Crossbar Scheduling”, in IEEE Micro, Micro's Top Picks from Hot Interconnects 16, Summer 2009. paper
G. Dimitrakopoulos, K. Galanopoulos, C. Mavrokefalidis, D. Nikolos, “Low-Power Leading Zero Counting and Anticipation Logic for High-Speed Floating Point Units”, in IEEE Transactions on VLSI Systems, July 2008. paper
G. Dimitrakopoulos, C. Mavrokefalidis, K. Galanopoulos, and D. Nikolos, “Sorter Based Permutation Units for Media-Enhanced Microprocessors”, in IEEE Transactions on VLSI Systems, vol. 15, no. 6, June 2007. paper
C. Efstathiou, H. T. Vergos, G. Dimitrakopoulos, and D. Nikolos, “Efficient Diminished-1 Modulo 2n+1 Multipliers”, in IEEE Transactions on Computers, vol. 54, no. 4, April 2005. paper
G. Dimitrakopoulos and D. Nikolos, “High-Speed Parallel-Prefix VLSI Ling Adders”, in IEEE Transactions on Computers, vol. 54, no. 2, pp. 225-231, February 2005. paper
G. Dimitrakopoulos and V. Paliouras, "A Novel Architecture and a Systematic Graph-Based Optimization Methodology for Modulo Multiplication", in IEEE Transactions on Circuits and Systems I, vol. 51, no. 2, pp. 354 - 370, February 2004. paper
Conference Papers
K. Alexandridis, C. Peltekis, D. Filippas, G. Dimitrakopoulos, "Floating-Point Multiply-Add with Approximate Normalization for Low-cost Matrix Engines", in IEEE International Conference on Electronics, Circuts and Systems (ICECS), Nov., 2024.
C. Peltekis, D. Filippas, G. Dimitrakopoulos, "Error Checking for Sparse Systolic Tensor Arrays" in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), April 2024. paper slides
C. Peltekis, K. Alexandridis, G. Dimitrakopoulos, "Reusing Softmax Hardware Unit for GELU Computation in Transformers" in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), April 2024. paper slides Best Student Paper Award
V. Titopoulos, K. Alexandridis, C. Peltekis, C. Nicopoulos, G. Dimitrakopoulos, "IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications", in Design Automation and Test in Europe (DATE), March 2024. arxiv
C. Peltekis, D. Filippas, G. Dimitrakopoulos, C. Nicopoulos, "The Case for Asymmetric Systolic Array Floorplanning", in IEEE International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Sept. 2023. paper
K. Rallis, G. Dimitrakopoulos, P. Dimitrakis, A. Rubio, S. Cotofana, I. Karafyllidis, G. Ch. Sirakoulis "Novel Circuit Design Methodology with Graphene Nanoribbon Based Devices" in IEEE International Conference on Nanotechnology (NANO), 2023. paper
C. Peltekis, D. Filippas, G. Dimitrakopoulos, C. Nicopoulos, "Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating", in International Conference on Circuits and Systems Technologies (MOCAST), June 2023. arxiv paper
G. Dimitrakopoulos, E. Kallitsounakis, Z. Takakis, A. Stefanidis, C. Nicopoulos, "Multi-Armed Bandits for Autonomous Test Application in RISC-V Processor Verification" , in International Conference on Circuits and Systems Technologies (MOCAST), June 2023. paper
D. Filippas, C. Peltekis, G. Dimitrakopoulos, C. Nicopoulos, "Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines" in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), June 2023. arxiv paper
C. Peltekis, D. Filippas, G. Dimitrakopoulos, C. Nicopoulos, D. Pnevmatikatos, ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining , in Design Automation and Test in Europe (DATE), Apr. 2023. arxiv paper
Y. Sazeides, A. Gerber, R. Gabor, A. Bramnik, G. Papadimitirou, D. Gizopoulos, C. Nicopoulos, G. Dimitrakopoulos, K. Patsidis, IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming , in ACM/IEEE International Symposium on Microarchitecture (MICRO), Oct. 2022. paper
C. Peltekis, D. Filippas, C. Nicopoulos, G. Dimitrakopoulos, "FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks" , in IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2022. paper
D. Filippas, C. Nicopoulos, G. Dimitrakopoulos, LeapConv: An Energy-efficient Streaming Convolution Engine with Reconfigurable Stride , in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2022. paper
G. Dimitrakopoulos, A. Psarras, C. Nicopoulos, "Virtual Channel Flow Control Across Mesochronous Clock Domains" , in IEEE Int. Conf. on Modern Circuits and Systems Technologies (MOCAST), June 2022. paper slides
D. Mangiras, G. Dimitrakopoulos, "Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment" , in IEEE Int. Conf. on Modern Circuits and Systems Technologies (MOCAST), July 2021. paper Best Student Paper Award
Y. Sazeides, A. Bramnik, R. Gabor, C. Nicopoulos, R. Canal, D. Konstantinou, G. Dimitrakopoulos, "2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD)", in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), Oct. 2020. paper
R. Karamani, I. Fyrigos, V. Ntinas, O. Liolis, G. Dimitrakopoulos, M. Altun, A. Adamatzky, M. R. Stan, G. Ch. Sirakoulis, "Memristive Learning Cellular Automata: Theory and Applications", in IEEE Int. Conf. on Modern Circuits and Systems Technologies (MOCAST), Germany, Sept 2020. paper
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K. Patsidis, C. Nicopoulos, G. Sirakoulis, G. Dimitrakopoulos, "RISC-V2: a Scalable RISC-V Vector Processor", in IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2020. paper
- T. Chatzinikolaou, I.-A. Fyrigos, R.-E. Karamani, V. Ntinas, G. Dimitrakopoulos, S. Cotofana, G. Sirakoulis "Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case", in IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2020. paper
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D. Konstantinou, C. Nicopoulos, J. Lee, G. Sirakoulis, G. Dimitrakopoulos, "SmartFork: Partitioned Multicast Allocation and Switching in Network-on-Chip Routers", in IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2020. paper
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A. Stefanidis, D. Mangiras, C. Nicopoulos, D. Chinnery and G. Dimitrakopoulos, "Design optimization by fine-grained interleaving of local netlist transformations in Lagrangian relaxation", in ACM International Symposium on Physical Design (ISPD), March, 2020. paper
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D. Mangiras, P. Mattheakis, P.-O. Ribet and G. Dimitrakopoulos, "Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV", in ACM International Symposium on Physical Design (ISPD), March, 2020. paper
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A. Stefanidis, D. Mangiras, C. Nicopoulos and G. Dimitrakopoulos, "Multi-Armed Bandits for Autonomous Timing-driven Design Optimization", in 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), July, 2019, pp. 17-22. paper
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Z. Takakis, D. Mangiras, C. Nicopoulos and G. Dimitrakopoulos, "Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage" in 4th International Verification and Security Workshop (IVSW), July 2019, pp. 61-66. paper
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R. Gabor, Y. Sazeides, A. Bramnik, A. Andreou, C. Nicopoulos, K. Patsidis, D. Konstantinou and G. Dimitrakopoulos, "Error-Shielded Register Renaming Subsystem for a Dynamically Scheduled Out-of-Order Core”, in Design Automation and Test in Europe (DATE), Mar. 2019. paper Best Paper Award
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D. Konstantinou, A. Psarras, G. Dimitrakopoulos, C. Nicopoulos, "Low-Power Dual-Edge-Triggered Synchronous Latency-Insensitive Systems", in Proc. IEEE Int. Conf. on Modern Circuits and Systems Technologies (MOCAST), Greece, May 2018. paper
I. Seitanidis, G. Dimitrakopoulos, P. Mattheakis, L. Masse-Navette, D. Chinnery, "Timing Driven Incremental Multi-Bit Register Composition Using a Placement Aware ILP formulation", in Proc. ACM/IEEE Design Automation Conference (DAC), USA, June 2017. paper
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M. Debnath, D. Konstatinou, C. Nicopoulos, G. Dimitrakopoulos, W-M Lin, and J. Lee "Low-Cost Congestion Management in Networks-on-Chip Using Edge and In-Network Traffic Throttling" in 2nd Int'l Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (HIPEAC-AISTECS), Sweden, 2017. paper
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A. Psarras, S. Moisidis, C. Nicopoulos and G. Dimitrakopoulos "RapidLink: a Network-on-Chip Architecture with Double-Data-Rate Links" , in IEEE Int'l Conference on Electronics, Circuits, and Systems (ICECS), France, Dec. 2016. paper
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I. Seitanidis, C. Nicopoulos and G. Dimitrakopoulos "PowerMax: An Automated Methodology for Generating Peak-Power Traffic in Networks-on-Chip" in 10th IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Sept. 2016, Japan. paper Best Paper Award Finalist
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A. Psarras, J. Lee, P. Mattheakis, C. Nicopoulos and G. Dimitrakopoulos "A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors" in ACM Great Lakes Symposium on VLSI (GLSVLSI) 2016, Boston, USA, May 2016. paper
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M. Paschou, A. Psarras, C. Nicopoulos and G. Dimitrakopoulos "CrossOver: Clock Domain Crossing under Virtual-Channel Flow Control" in Design Automation and Test in Europe (DATE), Dresden, Germany, Mar. 2016. paper
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A. Panteloukas, A. Psarras, C. Nicopoulos and G. Dimitrakopoulos "Timing Resilient Network-on-Chip Architectures" in IEEE International On-Line Testing Symposium (IOLTS), July 2015. paper
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A. Psarras, I. Seitanidis, C. Nicopoulos and G. Dimitrakopoulos "PhaseNoC: TDM Scheduling at the Virtual-Channel Level for Efficient Network Traffic Isolation" in Design Automation and Test in Europe (DATE), Grenoble, France, Mar. 2015. paper Best Paper Award
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I. Seitanidis, A. Psarras, E. Kalligeros, C. Nicopoulos, G. Dimitrakopoulos "ElastiNoC: A Self-Testable Distributed VC-based Network-on-Chip Architecture" in 8th IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Sept. 2014, Italy. paper
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I. Seitanidis, A. Psarras, G. Dimitrakopoulos, C. Nicopoulos "ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers", in Design Automation and Test in Europe (DATE), Mar. 2014. paper
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G. Dimitrakopoulos, I. Seitanidis, A. Psarras, K. Tsiouris, P. Matthaiakis, J. Cortadella "Hardware Primitives for the Synthesis of Multithreaded Elastic Systems", in Design Automation and Test in Europe (DATE), Mar. 2014. paper
G. Dimitrakopoulos, N. Georgiadis, C. Nicopoulos, E. Kalligeros, "Switch Folding: Network-on-Chip Routers with Time-Multiplexed Output Ports", in Design Automation and Test in Europe (DATE), Mar. 2013. paper
A. Roca, J. Flich, G. Dimitrakopoulos “DESA: Distibuted Elastic Switch Architecture for efficient Networks-on-FPGAs”, in the International Conference on Field-Programmable Logic and Applications (FPL 2012) Oslo, Norway, August 2012. paper
G. Dimitrakopoulos, E. Kalligeros, “Dynamic-Priority Arbiter and Multiplexer Soft Macros for On-Chip Networks Switches”, in ACM Design Automation and Test in Europe (DATE), Mar. 2012. paper
G. Dimitrakopoulos, E. Kalligeros, “Low-cost fault-tolerant switch allocator for network-on-chip routers”, Proc. of the 6th Interconnection Network Architecture, On-Chip Multi-Chip Workshop (INA-OCMC), Jan. 2012. paper
G. Dimitrakopoulos, C. Kachris, E. Kalligeros, “Scalable arbiters and multiplexers for on-FPGA interconnection networks”, in Proceedings of the 21st International Conference on Field-Programmable Logic and Applications (FPL 2011) Chania, Greece, September 2011. paper
G. Dimitrakopoulos and K. Galanopoulos, “Switch allocator for bufferless network-on-chip routers”, in Proceedings of the Fifth ACM Interconnection Network Architecture, On-Chip Multi-Chip Workshop (INA-OCMC) Heraklion, Greece, January 2011 paper
G. Dimitrakopoulos, N. Chrysos, K. Galanopoulos “Fast Arbiters for On-Chip Network Switches”, in IEEE International Conference on Computer Design (ICCD), Oct. 2008. paper
N. Chrysos and G. Dimitrakopoulos “Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation”, in IEEE Symposium on High-Performance Interconnects (HOT-Interconnects), pp. 67-74, Aug. 2008. paper
G. Dimitrakopoulos, C. Mavrokefalidis, K. Galanopoulos, and D. Nikolos, “An Energy-Delay Efficient Subword Permutation Unit”, in IEEE Conference on Application Specific Systems, Architectures, and Processors (ASAP), Sept. 2006. paper
G. Dimitrakopoulos, C. Mavrokefalidis, K. Galanopoulos, and D. Nikolos, “Fast Bit Permutation Unit for Media-Enhanced Microprocessor”, in IEEE International Symposium on Circuits and Systems (ISCAS), May 2006. paper
G. Dimitrakopoulos, D. G. Nikolos, H. T. Vergos, D. Nikolos, and C. Efstathiou, “New architectures for modulo 2n-1 adders”, in IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2005. paper
G. Dimitrakopoulos and D. Nikolos, “Closed-Form Bounds for Interconnect-Aware Minimum Delay Gate Sizing”, in International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2005), Lectures Notes in Computer Science, vol. 3728, pp. 308 - 317, Sep. 2005 paper
G. Dimitrakopoulos, P. Kolovos, P. Kalogerakis, and D. Nikolos, “Design of High-Speed Low-Power VLSI Parallel-Prefix Adders”, in Proceedings of the 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2004), Lectures Notes in Computer Science, vol. 3254, pp. 248 - 257, August 2004. paper
C. Efstathiou, H. Vergos, G. Dimitrakopoulos, and D. Nikolos, “Efficient Modulo 2n + 1 Tree Multipliers for Diminished-1 Operands”, in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (ICECS’ 03), December 2003, pp. 200-203. paper
G. Dimitrakopoulos, H. T. Vergos, D. Nikolos, and C. Efstathiou, "A Family of Parallel Prefix Modulo 2n-1 Adders’, in Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP’03), June 2003, pp. 326 - 336. paper
G. Dimitrakopoulos, X. Kavousianos, and D. Nikolos, “Virtual-Scan: A Novel Approach for Software-Based Self-Testing of Microprocessors”, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’03), May 2003, pp. 237-240. paper
G. Dimitrakopoulos, H. T. Vergos, D. Nikolos, and C. Efstathiou, “A Systematic Methodology for Designing Area-Time Efficient Parallel-Prefix Modulo 2n - 1 Adders”, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’ 03), May 2003, pp. 225-228. paper
G. Dimitrakopoulos, X. Kavousianos, and D. Nikolos, "Software-Based Self-testing of Microprocessors by Exploiting a Virtual Scan Path’, in the Supplement of the 4th European Dependable Computing Conference (EDCC-4), October 2002, pp. 23-24. paper
G. Dimitrakopoulos and V. Paliouras, “Graph-Based Optimization for a CSD-Enhanced RNS Multiplier”, in Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’02), August 2002, Volume III, pp. 648-651 paper
G. Dimitrakopoulos, D. Nikolos, and D. Bakalis, “Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register”, in Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW’02), July 2002, pp. 152-157. paper